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february 2010 doc id 16047 rev 2 1/48 48 L6563H high voltage start-up transition-mode pfc features on-board 700 v start-up source tracking boost function fast ?bidirectional? input voltage feedforward (1/v2 correction) interface for cascaded converter's pwm controller remote on/off control accurate adjustable output overvoltage protection protection against feedback loop disconnection (latched shutdown) inductor saturation protection low ( 100 a) start-up current 6 ma max. operating bias current 1% (@ t j = 25 c) internal reference voltage -600/+800 ma totem pole gate driver with active pull-down during uvlo applications pfc pre-regulators for: hi-end ac-dc adapter/charger iec61000-3-2 or jeita-miti compliant smps, in excess of 400 w figure 1. block diagram so - 16 so16 9)) 6 5 4 67$57(5 /(% 4 92/7$*( 5(*8/$725 89/2 9 08/7,3/,(5 ? ,qwhuqdo6xsso\%xv 9rowdjh uhihuhqfhv 9 9 9 9ff *' &6 *1' 08/7 ,19 3)&b2. 3:0b6723 =&' 'lvdeoh 293 89/2 'lvdeoh 4 6 5 ',6$%/( /b293 89/2 (uuru$psolilhu &203 ,ghdouhfwlilhu 9 9 9 293 p9 /b293 581 212))&rqwuro 6wduwhu 2)) 9 9 'hwhfwru =hur&xuuhqw 212))&rqwuro 0,5525 %8))(5 iurp &855(17 9 9)) 75$&.,1* %2267 7%2 '(7(&725 0$,16'523 3:0b /$ 7&+ /b293 9eldv 9 'lvdeoh , fkdujh +96 9 9)) 6 5 4 6 5 4 6 5 4 67$57(5 /(% 4 92/7$*( 5(*8/$725 89/2 9 08/7,3/,(5 ? ,qwhuqdo6xsso\%xv 9rowdjh uhihuhqfhv 9 9 9 9ff *' &6 *1' 08/7 ,19 3)&b2. 3:0b6723 =&' 'lvdeoh 293 89/2 89/2 'lvdeoh 4 6 5 ',6$%/( /b293 89/2 (uuru$psolilhu &203 ,ghdouhfwlilhu 9 9 9 293 p9 /b293 581 212))&rqwuro 6wduwhu 2)) 9 9 'hwhfwru =hur&xuuhqw 212))&rqwuro 0,5525 %8))(5 iurp &855(17 9 9)) 75$&.,1* %2267 7%2 '(7(&725 0$,16'523 3:0b /$ 7&+ /b293 9eldv 9 'lvdeoh , fkdujh +96 9 !-v www.st.com
contents L6563H 2/48 doc id 16047 rev 2 contents 1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.2 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3 pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4 electrical characteristi cs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5 typical electrical performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6 application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6.1 overvoltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6.2 feedback failure protection (ffp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6.3 voltage feedforward . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6.4 thd optimizer circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 6.5 tracking boost function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6.6 inductor saturation detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 6.7 power management/housekeeping functions . . . . . . . . . . . . . . . . . . . . . . 32 6.8 high-voltage start-up generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 7 application examples and ideas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 8 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 9 ordering codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 10 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
L6563H list of table doc id 16047 rev 2 3/48 list of table table 1. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 2. thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 3. pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 4. electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 5. summary of L6563H idle states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 6. so16 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 7. ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 8. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
list of figure L6563H 4/48 doc id 16047 rev 2 list of figure figure 1. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 figure 2. pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 3. typical system block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 4. ic consumption vs vcc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 5. ic consumption vs tj . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 6. vcc zener voltage vs tj . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 7. start-up and uvlo vs tj . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 8. feedback reference vs tj . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 9. e/a output clamp levels vs tj. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 10. uvlo saturation vs tj . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 11. ovp levels vs tj . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 12. inductor saturation threshold vs tj. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 13. vcs clamp vs tj . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 14. zcd sink/source capability vs tj . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 15. zcd clamp level vs tj . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 16. tbo clamp vs tj . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 17. vvff - vtbo dropout vs tj . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 18. iinv - itbo current mismatch vs tj . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 19. iinv - itbo mismatch vs itbo current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 8 figure 20. r discharge vs tj . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 21. line drop detection threshold vs tj . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 22. vmultpk - vvff dropout vs tj. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 23. pfc_ok threshold vs tj . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 24. pfc_ok ffd threshold vs tj . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 25. pwm_latch high saturation vs tj . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 26. run threshold vs tj. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 27. pwm_stop low saturation vs tj . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 0 figure 28. multiplier characteristics @ vff = 1 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 29. multiplier characteristics @ vff = 3 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 30. multiplier gain vs tj . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 31. gate drive clamp vs tj . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 32. gate drive output saturation vs tj . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 33. delay to output vs tj . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 34. start-up timer period vs tj . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 35. hv start voltage vs tj. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 36. vcc restart voltage vs tj . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 37. hv breakdown voltage vs tj . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 38. output voltage setting, ovp and ffp functions: internal block diagram . . . . . . . . . . . . . . 24 figure 39. voltage feedforward: squarer-divider (1/v2) block diagram and transfer characteristic . . 26 figure 40. rffcff as a function of 3rd harmonic distor tion introduced in the input current . . . . . . . 27 figure 41. thd optimizer circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 42. thd optimization: standard tm pfc controller (left side) and L6563H (right side) . . . . . . 28 figure 43. tracking boost block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 44. tracking output voltage vs input voltage characteristic with tbo . . . . . . . . . . . . . . . . . . . 31 figure 45. effect of boost inductor saturation on the mosfet current and detection method . . . . . . 31 figure 46. interface circuits that let dc-dc converter's controller ic drive L6563H in burst mode . . . . 32 figure 47. interface circuits that let the L6563H switch on or off a pwm controller. . . . . . . . . . . . . . . 33 figure 48. interface circuits for power up sequencing when dc-dc has the ss function . . . . . . . . . . . 33
L6563H list of figure doc id 16047 rev 2 5/48 figure 49. interface circuits for actual power-up sequencing (master pfc) . . . . . . . . . . . . . . . . . . . . 34 figure 50. brownout protection (master pfc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 51. high-voltage start-up generator: internal schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 52. timing diagram: normal power-up and power-down sequences . . . . . . . . . . . . . . . . . . . . 36 figure 53. high-voltage start-up behaviour during latch-off protection . . . . . . . . . . . . . . . . . . . . . . . . 37 figure 54. high-voltage start-up managing the dc-dc output short-circuit . . . . . . . . . . . . . . . . . . . . . . 37 figure 55. demonstration board evL6563H-100w, wide-ra nge mains: electrical schematic . . . . . . . 39 figure 56. L6563H 100 w tm pfc evaluation board: compliance to en61000-3-2 standard . . . . . . 40 figure 57. L6563H 100 w tm pfc evaluation board: compliance to jeita-miti standard . . . . . . . . 40 figure 58. L6563H 100 w tm pfc evaluation board: input current waveform @230-50 hz - 100 w 40 figure 59. L6563H 100w tm pfc evaluation board: input current waveform @100-50 hz - 100 w 40 figure 60. application board 90w-19v adapter with L6563H, l6599a, srk2000 . . . . . . . . . . . . . . . 41 figure 61. application board 130 w-12 v adapter with L6563H, l6599a, srk2000 . . . . . . . . . . . . . 42 figure 62. demonstration board evL6563H-650w wide-range mains: electrical schematics. . . . . . . 43 figure 63. so16 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
description L6563H 6/48 doc id 16047 rev 2 1 description the L6563H is a current-mode pfc controller operating in transition mode (tm) which embeds the same features existing in the l6563s with the addition of a high voltage start-up source. these functions make the ic especially suitable for applications that have to be compliant with energy saving regulations and where the pfc pre-regulator works as the master stage. the highly linear multiplier, along with a special correction circuit that reduces crossover distortion of the mains current, allows wide-range-mains operation with an extremely low thd even over a large load range. the output voltage is controlled by means of a voltage-mode error amplifier and an accurate (1% @tj = 25 c) internal volt age reference. loop's stability is optimized by the voltage feedforward function (1/v2 correction), which in this ic uses a proprietary technique that considerably improves line transient response as well in case of mains both drops and surges (?bidirectional?). additionally, the ic provides the option for tracking boost operation, i.e. the output voltage is changed tracking the mains voltage. the device includes disable functions suitable for remote on/off control too. in addition to an over voltage protection able to keep the output voltage under control during transient conditions, the ic is provided also with a protection against feedback loop failures or erroneous settings. other on-board protection functions allow that brownout conditions and boost inductor saturation can be safely handled. an interface with the pwm co ntroller of the dc-dc conver ter supplied by the pfc pre- regulator is provided: the purpose is to stop the operation of the converter in case of anomalous conditions for the pfc stage (feedback loop failure, boost inductor's core saturation, etc.) and to handle the pfc stage in case of light load for the dc-dc converter, to make it easier to comply with energy saving regulations (blue angel, energystar, energy2000, etc.). the totem-pole output stage, capable of 600 ma source and 800 ma sink current, is suitable for big mosfet or igbt drive. this, combined with the other features and the possibility to operate with st's proprietary fixed-off-time control, makes the device an excellent solution for smps up to 400 w that need to be compliant with en61000-3-2 and jeita-miti standards.
L6563H maximum ratings doc id 16047 rev 2 7/48 2 maximum ratings 2.1 absolute maximum ratings 2.2 thermal data table 1. absolute maximum ratings symbol pin parameter value unit v hvs 9 voltage range (referred to ground) -0.3 to 700 v i hvs 9 output current self-limited i hvs vcc 16 ic supply voltage (icc = 20 ma) self-limited v --- 1, 3, 7 max. pin voltage (i pin =1 ma) self-limited v --- 2, 4 to 6, 8, 11, 12 analog inputs and outputs -0.3 to 8 v i pwm_stop 11 max. sink current 3 ma i zcd 13 zero current detector max. current -10 (source) 10 (sink) ma table 2. thermal data symbol parameter value unit r thja max. thermal resistance, junction-to-ambient 120 c/w ptot power dissipation @t a = 50 c 0.75 w t j junction temperature operating range -40 to 150 c t stg storage temperature -55 to 150 c
pin connection L6563H 8/48 doc id 16047 rev 2 3 pin connection figure 2. pin connection !-v (63 #3 4"/ #/-0 -5,4 6&& 07-?,!4#( '$ '.$ :# $ 07-?34/0 0&#?/+ ).6 6cc 25 . .# (63 #3 4"/ #3 4"/ #/-0 -5,4 6&& 07-?,!4#( '$ '.$ :# $ 07-?34/0 0&#?/+ ).6 6cc 25 . .# table 3. pin description n name function 1inv inverting input of the error amplifier. the info rmation on the output voltage of the pfc pre- regulator is fed into the pin through a resistor divider. the pin normally features high impedance but, if the tracking boost function is used, an internal current generator programmed by tbo (pin 6) is activated. it sinks current from the pin to change the output voltage so that it tracks the mains voltage. 2comp output of the error amplifier. a compensation ne twork is placed between this pin and inv (pin 1) to achieve stability of the voltage control loop and ensure high power factor and low thd. to avoid uncontrolled rise of the output voltage at zero load, when the voltage on the pin falls below 2.4 v the gate driver output is inhibited (burst-mode operation). 3mult mains input to the multiplier. this pin is connec ted to the rectified mains voltage via a resistor divider and provides the sinusoidal reference to the current loop. the voltage on this pin is used also to derive the information on the rms mains voltage. 4cs input to the pwm comparator. the current flowin g in the mosfet is sensed through a resistor, the resulting voltage is applied to this pin and co mpared with an internal reference to determine mosfet?s turn-off. a second comparison level at 1.7 v detects abnormal currents (e.g. due to boost inductor saturation) and, on this occurrence, activates a safety procedure that temporarily stops the converter and limits the stress of the power components. 5vff second input to the multiplier for 1/v 2 function. a capacitor and a parallel resistor must be connected from the pin to gnd. they complete the internal peak-holding circuit that derives the information on the rms mains voltage. the voltage at this pin, a dc level equal to the peak voltage on pin mult (3), compensates the control loop gain dependence on the mains voltage. never connect the pin directly to gnd but with a resistor ranging from 100 k (minimum) to 2 m (maximum). 6tbo tracking boost function. this pin provides a buffered vff voltage. a resistor connected between this pin and gnd defines a current that is sunk from pin inv (1). in this way, the output voltage is changed proportionally to the mains volt age (tracking boost). if this function is not used leave this pin open.
L6563H pin connection doc id 16047 rev 2 9/48 7pfc_ok pfc pre-regulator output voltage monitoring/dis able function. this pin senses the output voltage of the pfc pre-regulator through a resist or divider and is used for protection purposes. if the voltage on the pin exceeds 2.5 v the ic st ops switching and restarts as the voltage on the pin falls below 2.4 v. however, if the voltage of the pin inv falls 40 mv below that one of the pin pfc_ok, a feedback failure is assumed. in this case the device is latched off and the pwm_latch (8) pin is asserted high. normal operation can be resumed only by cycling vcc bringing its value lower than 6v before to move up to turn on threshold. if the voltage on this pin is brought below 0.23 v the ic is shut down. to restart the ic the voltage on the pin must go above 0.27 v. this can be used as a remote on/off control input. 8pwm_latch output pin for fault signaling. during normal operation this pin features high impedance. if a feedback failure is detected (pfc_ok > 2.5 v a nd inv+40 mv < pfc_ok) the pin is asserted high. normally, this pin is used to stop the oper ation of the dc-dc converter supplied by the pfc pre-regulator by invoking a latched disable of its pwm controller. if not used, the pin is left floating. 9hvs high-voltage start-up. the pin, able to withstand 70 0 v, is to be tied directly to the rectified mains voltage. a 1 ma internal current source charges the capacitor connected between pin vcc (16) and pin gnd (14) until the voltage on the pin vcc reaches the start-up threshold, then it is shut down. normally, the generator is re- enabled when the vcc voltage falls below 6 v to ensure a low power throughput during short circ uit. otherwise, when a latched protection is tripped the generator is re-enabled as vcc re aches the uvlo threshold to keep the latch supplied. 10 n.c. not internally connected. provision for clearance on the pcb to meet safety requirements. 11 pwm_stop output pin for fault signaling. during normal oper ation this pin features high impedance. if the ic is disabled by a voltage below 0.8 v on pin run (12) the voltage on the pin is pulled to ground. normally, this pin is used to tempor arily stop the operation of the dc-dc converter supplied by the pfc pre-regulator by disabling its pwm controller. a typical usage of this function is brownout prot ection in systems where the pfc pre-r egulator is the master stage. if not used, the pin is left floating. 12 run remote on/off control. a voltage below 0.8 v s huts down (not latched) the ic and brings its consumption to a considerably lower level. pwm_ stop is asserted low. the ic restarts as the voltage at the pin goes above 0.88v. connect this pin to pin vff (5) either directly or through a resistor divider to use this function as brownout (ac mains undervoltage) protection. 13 zcd boost inductor?s demagnetization sensing input for transition-mode operation. a negative-going edge triggers mosfet?s turn-on. 14 gnd ground. current return for both the signal part of the ic and the gate driver. 15 gd gate driver output. the totem pole output stage is able to drive power mosfet?s and igbt?s with a peak current of 600 ma source and 800 ma sink. the high-level voltage of this pin is clamped at about 12 v to avoid excessive gate voltages. 16 vcc supply voltage of both the signal part of the ic and the gate driver. sometimes a small bypass capacitor (0.1 f typ.) to gnd might be useful to get a clean bias voltage for the signal part of the ic. table 3. pin description (continued) n name function
pin connection L6563H 10/48 doc id 16047 rev 2 figure 3. typical system block diagram !-v 6 inac 6 outdc 07-isturnedoffincaseof0&#gs ano malousoperationforsafety 0&#canbeturnedoffatlight loadtoeasecompliancewith ene rgysavingregulations ,( 07-or 2esonant #/.42/,,%2 0&#02% 2%'5,!4/2 $# $##/.6%24%2 6 inac 6 outdc 07-isturnedoffincaseof0&#gs ano malousoperationforsafety 0&#canbeturnedoffatlight loadtoeasecompliancewith ene rgysavingregulations ,( 07-or 2esonant #/.42/,,%2 0&#02% 2%'5,!4/2 $# $##/.6%24%2
L6563H electrical characteristics doc id 16047 rev 2 11/48 4 electrical characteristics t j = -25 to 125 c, v cc = 12 v, c o = 1 nf between pin gd and gnd, c ff = 1 f and r ff = 1 m between pin vff and gnd; unless otherwise specified table 4. electrical characteristics symbol parameter test co ndition min. typ. max. unit supply voltage vcc operating range after turn-on 10.3 22.5 v vcc on turn-on threshold (1) 11 12 13 v vcc off turn-off threshold (1) 8.7 9.5 10.3 v vcc restart vcc for resuming from latch ovp latched 5 6 7 v hys hysteresis 2.3 2.7 v v z zener voltage icc = 20 ma 22.5 25 28 v supply current i start-up start-up current before turn-on, vcc = 10 v 90 150 a i q quiescent current after turn-on, v mult = 1 v 4 5 ma i cc operating supply current @ 70 khz 5 6.0 ma i qdis idle state quiescent current v pfc_ok > v pfc_ok_s and v inv < v pfc_ok ? v ffd 180 280 a v pfc_ok < v pfc_ok_d or v run < v dis 1.5 2.2 ma i q quiescent current v pfc_ok > v pfc_ok_s or v comp < 2.3 v 2.2 3 ma high-voltage start-up generator v hv breakdown voltage i hv < 100 a 700 v v hvstart start voltage i vcc < 100 a 65 80 100 v i charge vcc charge current v hv > v hvstart , vcc > 3 v 0.55 0.85 1 ma i hv, on on-state current v hv > v hvstart , vcc > 3 v 1.6 ma v hv > v hvstart , vcc = 0 0.8 i hv, off off -state leakage current v hv = 400 v 40 a v ccrestart vcc restart voltage vcc falling 5 6 7 v ic latched off (1) 8.7 9.5 10.3 multiplier input i mult input bias current v mult = 0 to 3 v -0.2 -1 a v mult linear operation range 0 to 3 v v clamp internal clamp level i mult = 1 ma 9 9.5 v
electrical characteristics L6563H 12/48 doc id 16047 rev 2 vcs v mult output max. slope v mult =0 to 0.4 v, v vff = 0.8 v v comp = upper clamp 2.2 2.34 v/v k m gain (2) v mult = 1 v, v comp = 4 v 0.375 0.45 0.525 1/v error amplifier v inv voltage feedback input threshold t j = 25 c 2.475 2.5 2.525 v 10.3 v < vcc < 22.5 v (3) 2.455 2.545 line regulation vcc = 10.3 v to 22.5 v 2 5 mv i inv input bias current tbo open, v inv = 0 to 4 v -0.2 -1 a v invclamp internal clamp level i inv = 1 ma 8 9 v gv voltage gain open loop 60 80 db gb gain-bandwidth product 1 mhz i comp source current v comp = 4 v, v inv = 2.4 v 2 4 ma sink current v comp = 4 v, v inv = 2.6 v 2.5 4.5 ma v comp upper clamp voltage i source = 0.5 ma 5.7 6.2 6.7 v burst-mode voltage (3) 2.3 2.4 2.5 lower clamp voltage i sink = 0.5 ma (3) 2.1 2.25 2.4 current sense comparator i cs input bias current v cs = 0 1 a t leb leading edge blanking 100 150 250 ns td (h-l) delay to output 100 200 300 ns v csclamp current sense reference clamp v comp = upper clamp, v mult =1 v v vff = 1 v 1.0 1.08 1.16 v vcs ofst current sense offset v mult = 0, v vff = 3 v 40 70 mv v mult = 3 v, v vff = 3 v 20 boost inductor saturation detector v cs_th threshold on current sense (3) 1.6 1.7 1.8 v i inv e/a input pull-up current after v cs > v cs_th , before restarting 7 10 13 a pfc_ok functions i pfc_ok input bias current v pfc_ok = 0 to 2.6 v -0.1 -1 a v pfc_ok_c clamp voltage i pfc_ok = 1 ma 9 9.5 v v pfc_ok_s ovp threshold (1) voltage rising 2.435 2.5 2.565 v v pfc_ok_r restart threshold after ovp (1) voltage falling 2.34 2.4 2.46 v v pfc_ok_d disable threshold (1) voltage falling 0.12 0.35 v v pfc_ok_d disable threshold (1) voltage falling t j = 25 c 0.17 0.23 0.29 v table 4. electrical characteristics (continued) symbol parameter test co ndition min. typ. max. unit
L6563H electrical characteristics doc id 16047 rev 2 13/48 v pfc_ok_e enable threshold (1) voltage rising 0.15 0.38 v v pfc_ok_e enable threshold (1) voltage rising tj = 25 c 0.21 0.27 0.32 v v ffd feedback failure detection threshold (v pfc_ok -v inv ) v pfc_ok = v pfc_ok_s 15 40 65 mv v ffd feedback failure detection threshold (v pfc_ok -v inv ) v pfc_ok = v pfc_ok_s tj = 25 c 25 40 55 mv zero current detector v zcdh upper clamp voltage i zcd = 2.5 ma 5.0 5.7 v v zcdl lower clamp voltage i zcd = - 2.5 ma -0.3 0 0.3 v v zcda arming voltage (positive-going edge) 1.1 1.4 1.9 v v zcdt triggering voltage (negative-going edge) 0.5 0.7 0.9 v i zcdb input bias current v zcd = 1 to 4.5 v 1 a i zcdsrc source current capability -2.5 -4 ma i zcdsnk sink current capability 2.5 5 ma tracking boost function v dropout voltage v vff -v tbo i tbo = 0.2 ma -20 20 mv i tbo linear operation 0 0.2 ma i inv -i tbo current mismatch i tbo = 25 a to 0.2ma -5.5 1.0 % i inv -i tbo current mismatch i tbo = 25 a to 0.2ma t j = 25 c -4.0 +0 % v tboclamp clamp voltage (3) v vff = 4 v 2.9 3 3.1 v i tbo_pull pull-up current v tbo = 1 v v ff = v mult = 0 v 2 a pwm_stop i leak high level leakage current v pwm_stop = vcc 1 a v l low level i pwm_stop = 0.5 ma 1 v run function i run input bias current v run = 0 to 3 v -1 a v dis disable threshold (3) voltage falling 0.745 0.8 0.855 v v en enable threshold (3) voltage rising 0.845 0.88 0.915 v start-up timer t start_del start-up delay first cycle after wake-up 25 50 75 s table 4. electrical characteristics (continued) symbol parameter test co ndition min. typ. max. unit
electrical characteristics L6563H 14/48 doc id 16047 rev 2 t start timer period 75 150 300 s restart after v cs > v cs_th 150 300 600 voltage feedforward v vff linear operation range 0.8 3 v v dropout v multpk -v vff vcc < vcc on 800 mv vcc > or = to vcc on 20 v vff line drop detection threshold below peak value 40 70 100 mv v vff line drop detection threshold below peak value t j = 25 c 50 70 90 mv r disch internal discharge resistor t j = 25 c 7.5 10 12.5 k 520 v vff linear operation range 0.8 3 v pwm_latch i leak low level leakage current v pwm_latch = 0 -1 a v h high level i pwm_latch = -0.5 ma 4.5 v v h high level i pwm_latch = -0.25 ma vcc = vcc off 2.5 v v h high level i pwm_latch = -0.25 ma vcc = vcc off t j = 25 c 2.8 v gate driver v ol output low voltage i sink = 100 ma 0.6 1.2 v v oh output high voltage i source = 5 ma 9.8 10.3 v i srcpk peak source current -0.6 a i snkpk peak sink current 0.8 a t f voltage fall time 30 60 ns t r voltage rise time 45 110 ns v oclamp output clamp voltage i source = 5 ma; vcc = 20 v 10 12 15 v uvlo saturation vcc= 0 to v ccon , i sink = 2 ma 1.1 v 1. parameters tracking each other 2. the multiplier output is given by: 3. parameters tracking each other table 4. electrical characteristics (continued) symbol parameter test co ndition min. typ. max. unit () 2 vff v 5 . 2 comp v mult v k v cs v m cs_ofst ? ? ? + =
L6563H typical electrical performance doc id 16047 rev 2 15/48 5 typical electrical performance figure 4. ic consumption vs v cc figure 5. ic consumption vs t j ? 0.001 0.01 0.1 1 10 10 0 0 5 10 1 5 2 0 25 3 0 vc c [v ] icc [ma] vc c off vc c on co=1nf f =70khz tj = 25c ? 0.01 0.1 1 10 -50 -25 0 25 50 75 100 125 150 175 tj (c) ic current (ma) op e r a tin g qu ie sc e n t disabled or du r i n g ov p latched off before start up vcc=1 2v co = 1n f f =70khz figure 6. vcc zener voltage vs t j figure 7. start-up and uvlo vs t j ? 22 23 24 25 26 27 28 -50 -25 0 25 50 75 100 125 150 175 tj (c) v ? 6 7 8 9 10 11 12 13 -50 -25 0 25 50 75 100 125 150 175 tj (c) v vcc - o n vcc-off
typical electrical performance L6563H 16/48 doc id 16047 rev 2 figure 8. feedback reference vs t j figure 9. e/a output clamp levels vs t j ? 2. 4 2.45 2. 5 2.55 2. 6 -50 -25 0 25 50 75 100 125 150 175 tj (c) pi n inv (v ) vc c = 1 2v ? 0 1 2 3 4 5 6 7 -50 -25 0 25 50 75 100 125 150 175 tj (c) vcomp (v) u per c la m p l ower clamp v cc = 12v figure 10. uvlo saturation vs t j figure 11. ovp levels vs t j ? 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 -50 -25 0 25 50 75 100 125 150 175 tj (c) v vcc = 0 v ? 2.36 2.38 2.4 2.42 2.44 2.46 2.48 2.5 -50 -25 0 25 50 75 100 125 150 175 tj (c) pfc_ok levels (v) ovp th resta rt th
L6563H typical electrical performance doc id 16047 rev 2 17/48 figure 12. inductor saturation threshold vs t j figure 13. vcs clamp vs t j ? 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 -50 -25 0 25 50 75 100 125 150 175 tj (c ) cs pi n (v ) ? 1 1.1 1.2 1.3 1.4 -50 -25 0 25 50 75 100 125 150 175 tj (c) vc sx (v ) vcc = 12 v vcomp =upper clamp figure 14. zcd sink/source capability vs t j figure 15. zcd clamp level vs t j ? -8 -6 -4 -2 0 2 4 6 8 -50 -25 0 25 50 75 100 125 150 175 tj (c) izcdsrc (ma ) vcc = 12v source current si nk curren t ? -1 0 1 2 3 4 5 6 7 -50 -25 0 25 50 75 100 125 150 175 tj (c) v zcd pin (v ) vc c = 1 2v iz c d = 2.5mv upper clamp lower cl am p
typical electrical performance L6563H 18/48 doc id 16047 rev 2 figure 16. tbo clamp vs t j figure 17. v vff - v tbo dropout vs t j ? 2.5 2.75 3 3.25 3.5 -50 -25 0 25 50 75 100 125 150 175 tj (c ) v -5 -4 -3 -2 -1 0 1 2 3 4 5 -50-250255075100125150175 tj (c) mv figure 18. i inv - i tbo current mismatch vs t j figure 19. i inv - i tbo mismatch vs i tbo current ? -4 -3 .5 -3 -2 .5 -2 -1 .5 -1 -0 .5 0 -50 -25 0 25 50 75 100 125 150 175 tj (c) 10 0 *{i(in v) -i( tbo) }/i( tbo) [ % ] vc c = 12 v itb o = 2 5ua itbo = 200ua ? -3 -2.8 -2.6 -2.4 -2.2 -2 -1.8 -1.6 0 100 200 300 400 500 600 i( tb o) 100*{i(i nv )-i(tbo)}/i (tbo) [ % ] vcc = 1 2v tj = 25 c
L6563H typical electrical performance doc id 16047 rev 2 19/48 figure 20. r discharge vs t j figure 21. line drop detection threshold vs t j ? 0 2 4 6 8 10 12 14 16 18 20 -50 -25 0 25 50 75 100 125 150 175 tj (c) kohm ? 0 10 20 30 40 50 60 70 80 90 -50 -25 0 25 50 75 100 125 150 175 tj (c ) mv figure 22. v multpk - v vff dropout vs t j figure 23. pfc_ok threshold vs t j ? -2 -1.5 -1 -0.5 0 0. 5 1 1. 5 2 -50 -25 0 25 50 75 100 125 150 175 tj (c ) ? (m v) 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 -50 -25 0 25 50 75 100 125 150 175 tj (c) th (v ) on off
typical electrical performance L6563H 20/48 doc id 16047 rev 2 figure 24. pfc_ok ffd threshold vs t j figure 25. pwm_latch high saturation vs t j ? 0 10 20 30 40 50 60 -50 -25 0 25 50 75 100 125 150 175 tj (c) vffd th ( v) ? 4 5 6 7 8 9 10 -50 -25 0 25 50 75 100 125 150 175 tj (c) v vcc = 1 2 v isource =500ua isource =250ua figure 26. run threshold vs t j figure 27. pwm_stop low saturation vs t j ? 0.4 0.6 0.8 1 -50 -25 0 25 50 75 100 125 150 175 tj (c) v vcc = 1 2v o n o ff 0 0.05 0.1 0.15 0.2 0.25 -50 -25 0 25 50 75 100 125 150 175 tj (c) v vc c = 12 v is ink = 0 . 5m a
L6563H typical electrical performance doc id 16047 rev 2 21/48 figure 28. multiplier characteristics @ v ff = 1 v figure 29. multiplier characteristics @ v ff = 3 v ? 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 vm ul t ( v ) v cs (v) 4.5 v 3.5 v up p e r vo lt a g e cl am p 3.0 2.6 v 5.0v 4. 0v 5.5 vcomp ? 0 100 200 300 400 500 600 700 0 0.5 1 1.5 2 2.5 3 3.5 v mult (v ) vcs (mv) 2.6v 3.0v 4.5v 4.0v 3.5v 5.0v 5.5v upper vo ltage vcomp figure 30. multiplier gain vs t j figure 31. gate drive clamp vs t j ? 0. 2 0. 3 0. 4 0. 5 -50 -25 0 25 50 75 100 125 150 175 tj (c) gain (1/v ) vc c = 1 2v vc omp = 4v vmu lt = vff = 1 v ? 12.65 12.7 12.75 12.8 12.85 12.9 -50 -25 0 25 50 75 100 125 150 175 tj (c) v vcc = 20v
typical electrical performance L6563H 22/48 doc id 16047 rev 2 figure 32. gate drive output saturation vs t j figure 33. delay to output vs t j ? 0 2 4 6 8 10 12 -50 -25 0 25 50 75 100 125 150 175 tj (c) v low level high level 50 100 150 200 250 300 -50 -25 0 25 50 75 100 125 150 175 tj (c) t d (h - l ) (n s) vcc = 12v figure 34. start-up timer period vs t j figure 35. hv start voltage vs t j ? 0 50 100 150 200 250 300 350 400 450 -50 -25 0 25 50 75 100 125 150 175 tj (c) ti m e (us) fi r s t c i c l e timer aft e r oc p 0 20 40 60 80 100 -50-25 0 255075100125150175 tj (c) v
L6563H typical electrical performance doc id 16047 rev 2 23/48 figure 36. v cc restart voltage vs t j figure 37. hv breakdown voltage vs t j ? 0 2 4 6 8 10 12 14 -50 -25 0 25 50 75 100 125 150 175 tj (c) v fa lling ic c ? 500 550 600 650 700 750 800 -50 -25 0 25 50 75 100 125 150 175 tj (c) v
application information L6563H 24/48 doc id 16047 rev 2 6 application information 6.1 overvoltage protection normally, the voltage control loop keeps the output voltage vo of the pfc pre-regulator close to its nominal value, set by the ratio of the resistors r1 and r2 of the output divider. a pin of the device (pfc_ok) has been dedicated to monitor the output voltage with a separate resistor divider (r3 high, r4 low, see figure 38 ). this divider is selected so that the voltage at the pin reaches 2.5 v if the output voltage exceeds a preset value, usually larger than the maximum vo that can be expected. example: v o = 400 v, v ox = 434 v. select: r3 = 8.8 m ; then: r4 = 8.8 m 2.5/(434-2.5) = 51 k . when this function is triggered, the gate drive activity is immediately stopped until the voltage on the pin pfc_ok drops below 2.4 v. notice that r1, r2, r3 and r4 can be selected without any constraints. the unique criterion is that both dividers have to sink a current from the output bus which needs to be significantly higher than the bias current of both inv and pfc_ok pins. figure 38. output voltage setting, ovp and ffp functions: internal block diagram 6 6 6 ).6 $isable /60 %rror!mplifier #/-0 6 6 m6 ,?/60 0&#?/+ 6out &requency compensation 2a 2b 2 2a 2b 2 2 2 6 6 6 ).6 $isable /60 %rror!mplifier #/-0 6 6 m6 ,?/60 0&#?/+ 6out &requency compensation 2a 2b 2 2a 2b 2 2 2 !-v
L6563H application information doc id 16047 rev 2 25/48 6.2 feedback failure protection (ffp) the ovp function above described handles ?normal? over voltage conditions, i.e. those resulting from an abrupt load/line change or occurring at start-up. in case the overvoltage is generated by a feedback disconnection, for instance when the upper resistor of the output divider (r1) fails open, an additional circuitr y behind the pin pfc_ok detects the voltage gap with respect to pin inv. if the voltage gap is greater than 40 mv and the ovp is active, the ffp is triggered, the gate drive activity is immediately stopped, the device is shut down, its quiescent consumption is reduced below 180 a and the condition is latched as long as the supply voltage of the ic is above the uvlo threshold. at the same time the pin pwm_latch is asserted high. pwm_latch is an open source output able to deliver 2.8 v minimum with 0.25 ma load, intended for tripping a latched shutdown function of the pwm controller ic in the cascaded dc-dc converter, so that the entire unit is latched off. to restart the system it is necessary to recycle the input power, so that the vcc voltage of both the L6563H goes below 6v and that one of the pwm controller goes below its uvlo threshold. the pin pfc_ok doubles its function as a not-latched ic disable: a voltage below 0.23v shutdown the ic, reducing its consumption below 2 ma. in this case both pwm_stop and pwm_latch keep their high impedance status. to restart the ic simply let the voltage at the pin go above 0.27 v. note that these functions offer a complete protection against not only feedback loop failures or erroneous settings, but also against a failure of the protection itself. either resistor of the pfc_ok divider failing short or open or a pfc_ok pin floating results in shutting down the ic and stopping the pre-regulator. 6.3 voltage feedforward the power stage gain of pfc pre-regulators varies with the square of the rms input voltage. so does the crossover frequency fc of the overall open-loop gain because the gain has a single pole characteristic. this le ads to large trade-offs in the design. for example, setting the gain of the error amplifier to get fc = 20 hz @ 264 vac means having fc 4 hz @ 88 vac, resulting in a sl uggish control dynamics. additionally, the slow control loop causes large transient current flow during rapid line or load changes that are limited by the dynamics of the multiplier outpu t. this limit is consi dered when selecting the sense resistor to let the full load power pass under minimum line voltage conditions, with some margin. but a fixed current limit allows excessive power input at high line, whereas a fixed power limit requires the current limit to vary inversely with the line voltage. voltage feedforward can compensate for the gain variation with the line voltage and allow minimizing all of the above-mentioned issues. it consists of deriving a voltage proportional to the input rms voltage, feeding this voltage into a squarer/divider circuit (1/v2 corrector) and providing the resulting signal to the multiplier that generates the current reference for the inner current control loop (see figure 39 ).
application information L6563H 26/48 doc id 16047 rev 2 figure 39. voltage feedforward: squarer-divider (1/v2) block diagram and transfer characteristic in this way a change of the line voltage causes an inversely proportional change of the half sine amplitude at the output of the multiplier (if the line voltage doubles the amplitude of the multiplier output is halved and vice versa) so that the current reference is adapted to the new operating conditions with (ideally) no need for invoking the slow dynamics of the error amplifier. additionally, the loop gain is constant throughout the input voltage range, which improves significantly dynamic behavior at low line and simplifies loop design. actually, deriving a voltage proportional to the rms line voltage implies a form of integration, which has its own time constant. if it is too small the voltage generated is affected by a considerable amount of ripple at twice the mains frequency that causes distortion of the current reference (resulting in high thd and poor pf); if it is too large there is a considerable delay in setting the right amount of feedforward, resulting in excessive overshoot and undershoot of the pre-regulator's output voltage in response to large line voltage changes. clearly a trade-off was required. the L6563H realizes a new voltage feed forward that, with a technique that makes use of just two external parts, strongly minimizes this time constant trade-off issue whichever voltage change occurs on the mains, both surges and drops. a capacitor c ff and a resistor rff, both connected from the pin vff (#5) to ground, complete an internal peak-holding circuit that provides a dc voltage equal to the peak of the rectified sine wave applied on pin mult (#3). in this way, in case of sudden line voltage rise, c ff is rapidly charged through the low impedance of the internal diode; in case of line voltage drop, an internal ?mains drop? detector enables a low impedance switch which suddenly discharges cff avoiding long settling time before reaching the new voltage level. consequently, an acceptably low steady-state ripple and low current distortion can be achieved without any considerable undershoot or overshoot on the pre-regulator's output, like in systems with no feedforward compensation. the twice-mains-frequency (2 ? f l ) ripple appearing across c ff is triangular with a peak-to- peak amplitude that, with good approximation, is given by: !-v 08/7 5hfwlilhgpdlqv lghdoglrgh fxuuhqw uhihuhqfh 9fv[ 9 9)) & )) 5 )) ($rxwsxw 9 &203 9 08/7,3/,(5 /+ '(7(&725 0$,16'523 9 )) 9 08/7 9fv[ 9 &203 9 $fwxdo ,ghdo 08/7 5hfwlilhgpdlqv lghdoglrgh fxuuhqw uhihuhqfh 9fv[ 9 9)) & )) 5 )) ($rxwsxw 9 &203 9 08/7,3/,(5 /+ '(7(&725 0$,16'523 08/7 5hfwlilhgpdlqv lghdoglrgh fxuuhqw uhihuhqfh 9fv[ 9 9)) & )) 5 )) ($rxwsxw 9 &203 9 08/7,3/,(5 /+ '(7(&725 0$,16'523 9 )) 9 08/7 9fv[ 9 &203 9 $fwxdo ,ghdo 9 )) 9 08/7 9fv[ 9 &203 9 $fwxdo ,ghdo ff ff l multpk ff c r f 4 1 v 2 v + =
L6563H application information doc id 16047 rev 2 27/48 where f l is the line frequency. the amount of 3rd harmonic distortion introduced by this ripple, related to the amplitude of its 2 ? f l component, is: figure 40 shows a diagram that helps choose the time constant r ff c ff based on the amount of maximum desired 3rd harmonic distortion. always connect r ff and c ff to the pin, the ic does not work properly if the pin is either left floating or connected directly to ground. figure 40. r ff c ff as a function of 3rd harmonic distortion introduced in the input current the dynamics of the voltage feedforward input, th at is the output of th e multiplier, is limited downwards at 0.8 v (see figure 39 ), so that cannot increase any more if the voltage on the vff pin is below 0.8 v. this helps to prevent excessive power flow when the line voltage is lower than the minimum specified value. 6.4 thd optimizer circuit the L6563H is provided with a special circui t that reduces the conduction dead-angle occurring to the ac input current near the zero-crossings of the line voltage (crossover distortion). in this way the thd (total harmon ic distortion) of the current is considerably reduced. a major cause of this distortion is the inability of the system to transfer energy effectively when the instantaneous line voltage is very lo w. this effect is magnified by the high- frequency filter capacitor placed after the br idge rectifier, which re tains some residual voltage that causes the diodes of the bridge rectifier to be reverse-biased and the input current flow to temporarily stop. to overcome this issue the device forces the pfc pre-regulator to process more energy near the line voltage zero-crossings as compared to that commanded by the control loop. this results in both minimizing the time interval where energy transfer is lacking and fully discharging the high-frequency filter capacitor after the bridge. figure 41 shows the internal block diagram of the thd optimizer circuit. ff ff l 3 c r f 2 100 % d = ? d % 3 0.1110 0.01 0.1 1 10 f = 50 hz l f = 60 hz l r c [s] ff ff
application information L6563H 28/48 doc id 16047 rev 2 figure 41. thd optimizer circuit figure 42. thd optimization: standard tm pfc controller (left side) and L6563H (right side) !-v 08/7 &203 w #9df #9df!9df w w wr3:0 frpsdudwru 08/7,3/,(5 2))6(7 *(1(5$725 w 9)) 9 w w 08/7 &203 w #9df #9df!9df w w wr3:0 frpsdudwru 08/7,3/,(5 2))6(7 *(1(5$725 w 9)) 9 w w 08/7 &203 w #9df #9df!9df w w wr3:0 frpsdudwru 08/7,3/,(5 08/7,3/,(5 2))6(7 *(1(5$725 2))6(7 *(1(5$725 w 9)) 9 9 w w ? imains vdrain imain s vdrain in p ut c urr e nt input current m os fet's d rai n vol t a ge m osfe t's dra i n vol t ag e rectified mains voltage rectified mains voltage input current input current
L6563H application information doc id 16047 rev 2 29/48 essentially, the circuit artificially increases th e on-time of the power switch with a positive offset added to the output of the multiplier in the proximity of the line voltage zero-crossings. this offset is reduced as the instantaneous line voltage increases, so that it becomes negligible as the line voltage moves toward the top of the sinusoid. furthermore the offset is modulated by the voltage on the vff pin (see ?v oltage feedforward? section) so as to have little offset at low line, where energy transfer at zero crossings is typically quite good, and a larger offset at high line where the energy transfer gets worse. the effect of the circuit is shown in figure 42 , where the key waveforms of a standard tm pfc controller are compared to those of this chip. to take maximum benefit from the thd optimizer circuit, the high-frequency filter capacitor after the bridge rectifier should be minimized, compatibly with emi filtering needs. a large capacitance, in fact, introduces a conduction dea d-angle of the ac input current in itself - even with an ideal energy transfer by the pfc pre-regulator - thus reducing the effectiveness of the optimizer circuit. 6.5 tracking boost function in some applications it may be advantageous to regulate the output voltage of the pfc pre- regulator so that it tracks the rms input vo ltage rather than at a fixed value like in conventional boost pre-regulato rs. this is commonly referred to as ?tracking boost? or ?follower boost? approach. with the L6563H this can be realized by connecting a resistor (rt) between the tbo pin and ground. the tbo pin presents a dc level equal to the peak of the mult pin voltage and is then representative of the mains rms voltag e. the resistor defines a current, equal to v(tbo)/rt, that is internally 1:1 mirrored and sunk from pin inv (#1) input of the L6563H's error amplifier. in this way, when the ma ins voltage increases the voltage at tbo pin increases as well and so does the current flowing through the resistor connected between tbo and gnd. then a larger current is sunk by inv pin and the output voltage of the pfc pre-regulator is forced to get higher. obviously, the output voltage moves in the opposite direction if the input voltage decreases. to avoid undesired output voltage rise should the mains voltage exceed the maximum specified value, the voltage at the tbo pin is clamped at 3v. by properly selecting the multiplier bias it is possible to set the ma ximum input voltage above which input-to-output tracking ends and the output voltage becomes constant. if this function is not used, leave the pin open: the device regulates a fixed output voltage. starting from the following data: vin 1 = minimum specified input rms voltage; vin 2 = maximum specified input rms voltage; vo 1 = regulated output voltage @ vin = vin 1 ; vo 2 = regulated output voltage @ vin = vin 2 ; vox = absolute maximum limit for the regulated output voltage; to set the output voltage at the desired va lues use the following design procedure:
application information L6563H 30/48 doc id 16047 rev 2 1. determine the input rms voltage vinclamp that produces vo = vox: and choose a value vin x such that vin 2 vinx < vinclamp. this re sults in a limitation of the output voltage range below vox (it is equal vox if one chooses vin x = vin clamp ) 2. determine the divider ratio of the mult pin (#3) bias: and check that at minimum mains voltage vin1 the peak voltage on pin 3 is greater than 0.65 v. 3. determine r1, the upper resistor of the output divider, for instance 3 m . 4. calculate the lower resistor r2 of the output divider a nd the adjustment resistor rt: 5. check that the maximum current sourced by the tbo pin (#6) does not exceed the maximum specified (0.2 ma): figure 43 shows the internal block diagra m of the tracking boost function. figure 43. tracking boost block 1 1 2 2 2 1 2 1 clamp vin vo vo vo vox vin vo vo vo vox vin ? ? ? ? ? ? ? = x vin 2 3 k ? = ()( ) ? ? ? ? ? ? ? ? ? ? ? ? = ? ? ? ? ? ? ? ? = 1 2 1 2 t 1 2 2 1 1 2 vo vo vin vin 1 r k 2 r vin 5 . 2 vo vin 5 . 2 vo vin vin 1 r 5 . 2 2 r 3 t max tbo 10 2 . 0 r 3 i ? ? = !-v 6 ).6 %rror!mplifier #/-0 -)22/2 "5&& %2 from #522%.4 6 6&& 42!#+).' "//34 4"/ to-ultiplier 6 /54 2 4 ) 4"/ ) 4"/ 2 2 6 ).6 %rror!mplifier #/-0 -)22/2 "5&& %2 from #522%.4 6 6&& 42!#+).' "//34 4"/ to-ultiplier 6 /54 2 4 ) 4"/ ) 4"/ 2 2
L6563H application information doc id 16047 rev 2 31/48 figure 44. tracking output voltage vs input voltage characteristic with tbo 6.6 inductor satur ation detection boost inductor's hard saturation may be a fatal event for a pfc pre-regulator: the current up- slope becomes so large (50-100 times steeper, see figure 45 ) that during the current sense propagation delay the current may reach abnormally high values. the voltage drop caused by this abnormal current on the sense resistor reduces the gate-to-source voltage, so that the mosfet may work in the active region and dissipate a huge amount of power, which leads to a catastrophic failure after few switching cycles. however, in some applications such as ac-dc adapters, where the pfc pre-regulator is turned off at light load for energy saving reasons, even a well-designed boost inductor may occasionally slightly saturate when the pfc stage is restarted because of a larger load demand. this happens when the restart occurs at an unfavorable line voltage phase, i.e. when the output voltage is significantly below th e rectified peak voltage. as a result, in the boost inductor the inrush current coming from the bridge rectifier adds up to the switched current and, furthermore, there is little or no voltage available for demagnetization. to cope with a saturated inductor, the L6563H is provided with a second comparator on the current sense pin (cs, pin 4) that stops the ic if the voltage, normally limited within 1.1 v, exceeds 1.7 v. after that, the ic attempts to restart by the in ternal starter circuitry; the starter repetition time is twice the nominal value to guarantee lower stress for the inductor and boost diode. hence, the system safety is considerably increased. figure 45. effect of boost inductor saturation on the mosfet current and detection method !-v 9r 9r 9lq 9lq 9lq [ 9lq 9lq 9r [ 9r 9r 9r 9r 9lq 9lq 9lq 9lq [ 9lq [ 9lq 9lq 9lq 9r [ 9r [ 9r 9r
application information L6563H 32/48 doc id 16047 rev 2 6.7 power management/housekeeping functions a special feature of this ic is that it facilitates the implem entation of the ?housekeeping? circuitry needed to co-ordinate the operation of the pfc stage to that of the cascaded dc- dc converter. the functions realized by the housekeeping circuitry ensure that transient conditions like power-up or power down sequencing or failures of either power stage be properly handled. this device provides some pins to do that. one communication line between the ic and the pwm controller of the cascaded dc-dc converter is the pin pwm_latch ( figure 47 b ), which is normally open (high impedance) when the pfc works properly, and goes high if it loses control of the output voltage (because of a feedback loop disconnection) with the aim of latching off the pwm controller of the ca scaded dc-dc converter as well (see ?feedback failure protection? section for more details). a second communication line can be established via the disable function included in the pfc_ok pin (see ?feedback failure protection? se ction for more details). typically this line is used to allow the pwm controller of the cascaded dc-dc converter to drive in burst mode operation the L6563H in case of light load a nd to minimize the no-load input consumption. interface circuits like those are shown in figure 46 . figure 46. interface circuits that let dc-dc converter's controller ic drive L6563H in burst mode the third communication line is the pin pwm_stop (#11), which works in conjunction with the pin run (#12). the purpose of the pwm_stop pin is to inhibit the pwm activity of both the pfc stage and the cascaded dc-dc converter. the pin is an open collector, normally open, that goes low if the device is disabled by a voltage lower than 0.8 v on the run pin. it is important to point out that this function wo rks correctly in systems where the pfc stage is the master and the cascaded dc-dc converter is the slave or, in other words, where the pfc stage starts first, powers both controllers an d enables/disables the operation of the dc-dc stage. the pin run can be used to start and stop the main converter. in the simplest case, to enable/disable the pwm controller the pin pwm_stop can be connected to the output of the error amplifier ( figure 47 a ). !-v /$ 3)&b6723 /+ 581 3)&b2. / 3)&b6723 /+ 581 3)&b2. /$ 3)&b6723 /+ 581 3)&b2. /$ 3)&b6723 /+ 581 3)&b2. / 3)&b6723 /+ 581 3)&b2. / 3)&b6723 /+ 581 3)&b2.
L6563H application information doc id 16047 rev 2 33/48 figure 47. interface circuits that let the L6563H switch on or off a pwm controller if the chip is provided with a soft-start pin, it is possible to delay the start-up of the dc-dc stage with respect to that of the pfc stage, which is often desired, as described in figure 48 . an underlying assumption in order for that to work properly is that the uvlo thresholds of the pwm controller are certainly higher than those of the L6563H. figure 48. interface circuits for power up sequencing when dc-dc has the ss function if this is not the case or it is not possible to achieve a start-up delay long enough (because this prevents the dc-dc stage from starting up correctly) or, simply, the pwm controller is devoid of soft start, the arrangement of figure 49 lets the dc-dc converter start-up when the voltage generated by the pfc stage reaches a preset value. the technique relies on the uvlo thresholds of the pwm controller. !-v /+ 581 3:05(6 frqwuroohu 3:0b6723 ; 8&[; 8& [; / $; / ; / $; ru 21 2)) dqrwodwfkhg /+ 3:05(6 frqwuroohu 3:0b/$7&+ ; /$; / ; / $; eodwfkhg /+ 581 3:05(6 frqwuroohu 3:0b6723 ; 8&[; 8& [; / $; / ; / $; ru 21 2)) dqrwodwfkhg /+ 581 3:05(6 frqwuroohu 3:0b6723 ; 8&[; 8& [; / $; / ; / $; ru 21 2)) dqrwodwfkhg /+ 3:05(6 frqwuroohu 3:0b/$7&+ ; /$; / ; / $; eodwfkhg /+ 3:05(6 frqwuroohu 3:0b/$7&+ ; /$; / ; / $; eodwfkhg !-v /+ 581 3:05(6 frqwuroohu 3:0b6723 ; /$; / ; / $; 21 2)) 66 & 66 /+ 581 3:05(6 frqwuroohu 3:0b6723 ; /$; / ; / $; 21 2)) 66 & 66
application information L6563H 34/48 doc id 16047 rev 2 figure 49. interface circuits for actual power-up sequencing (master pfc) another possible use of the run and pwm_stop pins (again, in systems where the pfc stage is the master) is the brownout protection, thanks to the hysteresis provided. the brownout protection is basically a not-latche d device shutdown function that is activated when a condition of mains undervoltage is detected. this condition may cause overheating of the primary power section due to an excess of rms current. brownout can also cause the pfc pre-regulator to work open loop and this could be dangerous to the pfc stage itself and the downstream converter, should the input voltage return abruptly to its rated value. another problem is the spurious restarts that may occur during converter power down and that cause the output voltage of the converter not to decay to zero monotonically. for these reasons it is usually preferable to shutdown the unit in case of brownout. ic shutdown upon brownout can be easily realized as shown in figure 50 . the scheme on the left is of general use, that one on the righ t can be used if the bias levels of the multiplier and the r ff c ff time constant are compatible with the specified brownout level and with the specified holdup time respectively . in this latest case, an additional resistor voltage divider and one capacitor are not needed. in table 1 it is possible to find a summary of all of the above mentioned working conditions that cause the device to stop operating. figure 50. brownout protection (master pfc) !-v 6xsso\udlo n 7 %&& %& 9= /+ 2)) 21 3:0 frq wuroohu /$ ; 8& [; 8& [; / ; /; ; 581 9ff 3:0b6723 +9exv 9ffb 2ii 9=9ff pd[ 3)&b2. 6xsso\udlo n 7 %&& %& 9= /+ 2)) 21 3:0 frq wuroohu /$ ; 8& [; 8& [; / ; /; ; 581 9ff 3:0b6723 +9exv 9ffb 2ii 9=9ff pd[ 3)&b2. ? ru n run L6563H L6563H 12 12 ru n run L6563H L6563H 12 12
L6563H application information doc id 16047 rev 2 35/48 6.8 high-voltage start-up generator figure 51 shows the internal schematic of the high-voltage start-up generator (hv generator). it is made up of a high-voltage n-channel fet, whose gate is biased by a 15 m resistor, with a temperature-compensated current generator connected to its source. figure 51. high-voltage start-up generator: internal schematic the hv generator is physically located on a separate chip, made with bcd off-line technology able to withstand 700 v, controlled by a low-voltage chip, where all of the control functions reside. with reference to the timing diagram of figure 52 , when power is first applied to the converter the voltage on the bulk capacitor (v in) builds up and, at about 80 v, the hv generator is enabled to operate (hv_en is pulled high) so that it draws about 1 ma. this current, minus the device's consumption, charges the bypass capacitor connected from pin vcc (16) to ground and makes its voltage rise almost linearly. !-v /+ 0 7 *1' +96 9ff , fkdujh 9ffb2. , +9 &21752/ +9b(1
application information L6563H 36/48 doc id 16047 rev 2 figure 52. timing diagram: normal power-up and power-down sequences as the vcc voltage reaches the start-up threshold (12 v typ.) the low-voltage chip starts operating and the hv generator is cut off by th e vcc_ok signal asserted high. the device is powered by the energy stored in the vcc capaci tor until the self-supply circuit (we assume that it is made with an auxilia ry winding in the transformer of the cascaded dc-dc converter and a steering diode) develops a voltage high enough to sustain the operation. the residual consumption of this circuit is just the one on the 15 m resistor (10 mw at 400 vdc), typically 50-70 times lower, under the same conditions, as compared to a standard start-up circuit made with external dropping resistors. at converter power-down the dc-dc converter loses regulation as soon as the input voltage is so low that either peak current or maximu m duty cycle limitation is tripped. vcc then drops and stops ic activity as it falls below the uvlo threshold (9.5 v typ.). the vcc_ok signal is de-asserted as the vcc voltage goes below a threshold vccrestart located at about 6 v. the hv generator can now restart. however, if vin < vhvstart, hv_en is de-asserted too and the hv generator is disabled. this prevents converter's restart attempts and ensures monotonic output voltage decay at power-down in systems where brownout protection (see the relevant section) is not used. if the device detects a fault due to feedback failure the pin pwm_latch is asserted high (see ?feedback failure protection? section for more details) and, in order to maintain alive this signal to be provided to the dc-dc conver ter, the internal vccrestart is brought up to over the vccoff (turn-off thre shold). as a result, shown in figure 53 , the voltage at pin vcc, oscillates between its turn-on an d turn-off thresholds until th e hv bus is recycled and drops below the start up threshold of the hv generator. the high voltage start-up circuitry is capable to guarantee a safe behavior in case of short circuit present on the dc-dc ou tput when the vcc of both controllers are generated by the same auxiliary winding. the figure 54 shows how the pfc manages the vcc cycling and the associated power transfer. at short circuit th e auxiliary circuit is no longer able to sustain the vcc which start dropping; reaching its vcco ff threshold the ic st ops switching, reduces !-v 9ff slq *' slq +9b(1 9ff 21 9ff 2)) 9ff uhvwduw w w w w 9+9 9 +9vwduw , fkdujh p$ w w 9ffb2. 3rzhurq 3rzhurii 1rupdo rshudwlrq 'fgforvhvuhjxodwlrqkhuh ,qsxwvrxufhlvuhpryhgkhuh %xonfdsyrowdjh +9frqqhfwhgwr uhfwlilhglqsxwyrowdjh 5hfwlilhglqsxwyrowdjh +9frqqhfwhgwrexonfds 9ff slq *' slq +9b(1 9ff 21 9ff 2)) 9ff uhvwduw w w w w 9+9 9 +9vwduw , fkdujh p$ w w 9ffb2. 3rzhurq 3rzhurii 1rupdo rshudwlrq 'fgforvhvuhjxodwlrqkhuh ,qsxwvrxufhlvuhpryhgkhuh %xonfdsyrowdjh +9frqqhfwhgwr uhfwlilhglqsxwyrowdjh 5hfwlilhglqsxwyrowdjh +9frqqhfwhgwrexonfds
L6563H application information doc id 16047 rev 2 37/48 consumption and drops more until the vccrestart threshold is tripped. now, the high voltage start-up generator restarts and when the vcc crosses again its turn on threshold the ic starts switching. in this manner the power is transferred from ma ins to pfc output only during a short time for each trep cycle. figure 53. high-voltage start-up behaviour during latch-off protection figure 54. high-voltage start-up managing the dc-dc output short-circuit !-v *' slq 9lq 9ff 21 w w w w 9ff 2)) 3:0b/$7&+ slq 9ff uhvwduw 9 +9vwduw +9jhqhudwrulvwxuqhgrq 'lvdeohodwfklvuhvhwkhuh +9b(1 )dxowrffxuvkhuh +9jhqhudwruwxuqrqlvglvdeohgkhuh ,qsxwvrxufhlvuhpryhgkhuh w 9ff slq *' slq 9lq 9ff 21 w w w w 9ff 2)) 3:0b/$7&+ slq 9ff uhvwduw 9 +9vwduw +9jhqhudwrulvwxuqhgrq 'lvdeohodwfklvuhvhwkhuh +9b(1 )dxowrffxuvkhuh +9jhqhudwruwxuqrqlvglvdeohgkhuh ,qsxwvrxufhlvuhpryhgkhuh w 9ff slq !-v 9ff slq *' slq 9ffb2. 9ff 21 9ff 2)) 9ff uhvwduw , fkdujh p$ 6kruwflufxlwrffxuvkhuh w w w w 7 uhs 9ff slq *' slq 9ffb2. 9ff 21 9ff 2)) 9ff uhvwduw , fkdujh p$ 6kruwflufxlwrffxuvkhuh w w w w 7 uhs
application information L6563H 38/48 doc id 16047 rev 2 table 5. summary of L6563H idle states condition caused or revealed bey ic behavior restart condition typical ic consumption pwm_latch status pwm_stop status uvlo vcc < vcc off disabled vcc > vcc on 90 a off high feedback disconnected pfc_ok > v pfc_ok_s and inv < pfc_ok - 40mv latched vcc < vcc restart then vcc > vcc on 180 a high high standby pfc_ok < v pfc_ok_d stop switching pfc_ok > v pfc_ok_e 1.5 ma off high ac brownout run < v dis run > v en 1.5 ma off low ovp pfc_ok > v pfc_ok_s pfc_ok < v pfc_ok_r 2.2 ma off high low consumption comp < 2.4v burst mode comp > 2.4v 2.2 ma off high saturated boost inductor vcs > v cs_th doubled tstart auto restart 2.2 ma off high
L6563H application examples and ideas doc id 16047 rev 2 39/48 7 application examples and ideas figure 55. demonstration board evL6563H-100w, wide-range mains: electrical schematic !-v 5 0 5 0 b a a ' *% 8- & 1 & 1 / +) <57 5 . ) )8 6( $ -3 :,5 (-80 3(5 ,1 68/$7(' & 1 5 5 & 1 9 / 65: 34;;; 9 ' 677+/ 5 17& 56 & x) 9 & 1 9df ,1 9 &203 08 /7 &6 9)) 7%2 3)& 2. 3:0/$7&+ 3:06723 58 1 =& ' *1' *' 9&& +96 1& 8 /+ 5 . 4 67)101 - &21 ' 1 5 0 5 0 5 . 5 0 5 . 5 . 5 0 5 5 5 . 5 5 5 . 5 5 5 0 5 . 5 0 5 . & 1 & x) & s & 1 & 1 & 1 & 1 5 . 5 0 *1' 9&& - 0.'6 3:0b/$7&+ 3:0b6723 212)) +6 +($76,1 . 5 . - 0.'6 & x )9 5 0 5 5 5 5 ' // ' %=;&
application examples and ideas L6563H 40/48 doc id 16047 rev 2 figure 56. L6563H 100 w tm pfc evaluation board: compliance to en61000-3-2 standard figure 57. L6563H 100 w tm pfc evaluation board: compliance to jeita-miti standard vin = 230 vac - 50 hz, pout = 100 w thd = 7.58%, pf = 0.979 vin = 100 vac - 50 hz, pout = 100 w thd = 2.5%, pf = 0.997 figure 58. L6563H 100 w tm pfc evaluation board: input current waveform @230-50 hz - 100 w load figure 59. L6563H 100w tm pfc evaluation board: input current waveform @100 v-50 hz - 100 w load ? 0.0001 0.001 0. 01 0.1 1 1 3 5 7 9 111315171921232527293133353739 harmonic order [n] harmonic curr ent [a] measured value en61 000 -3- 2 cl as s -d l i m it s 0.0001 0.001 0. 0 1 0.1 1 10 1 3 5 7 9 11 13 15171921 2325272931 33353739 harmonic order [n] harmonic current [a] measured value jeita-miti class-d limits
L6563H application examples and ideas doc id 16047 rev 2 41/48 figure 60. application board 90w-19v adapter with L6563H, l6599a, srk2000 & x)9 & 1 5 0 5 0 5 0 5 . b a a ' *%8- & 1< & 1< 5 . & 1; / $ & 3) / 65: 34 ;;;9 5 . -3; ) )8 6( 7 $ & 1 5 . 5 . 5 . 5 5 ' // ' // ' // ' // ' %=9& & x) 9< ;) ' %=9% 4 6731) / ' // 5 10 & 19 ' // 5 . & x)9<;) ' 677+/ 5 17& 5 6 & x 9 4 6731) / & x)9 ' // 5 5 & 1 & x ) 9 5 . 5 . 5 0 5 . -3 - 0.'6 5 5 5 5 & 1) 5 0 & x) 9 +6 5 5 5 10 9df 5 5 5 10 5 . 5 5 ' // 4 %&& 8 7/ $,= 5 5 5 5 & 1) & 3) 5 . 4 67)10 1 & x ) 9 ' 1 5 . 5 . 5 0 & 10 5 0 5 . 5 . 5 . 5 0 5 5 5 5 5 . & 1 5 5 5 10 & 1; 5 . 5 0 5 0 4 %&& 5 . ' // 5 5 ' 10 & x) 7 $ $ & 3) & 1 ' // & 1 & 1 & 1 -3 & 1 5 . 5 . 5 . +6 +($76,1 . 4 67310)3 / x & 1 5 . 6*1' (1 '96 '96 *' 3*1' *' 9&& 8 65. 4 10 ' %=9% 4 67310)3 & x) 9< ;) 5 . +6 +($76,1 . 5 . 5 0 ' // -3; & 1 & 1 5 . & 1 & 10 ' // 5 . -3 ' 6736/$ 5 . & x ) 9 & 1< & 1) 5 . - 0.'6 5 . & 1 5 5 & 1 5 5 5 . & 1< ' // 5 10 & x)9 & 1 5 . 5 . 5 . 5 10 & 10 8 6)+ $ 5 5 ,19 &203 08/7 &6 9)) 7% 2 3)&2 . 3:0/ $7&+ 3:06723 581 =& ' *1' *' 9&& +96 1& 8 / + & 1 5 5 5 . 5 5 4 %&& &66 '(/$< &) 5)0,1 67%< ,6(1 /,1( *1' /9* 9&& 1& 287 +9* 9%22 7 ',6 3)&6723 8 / $ !-v
application examples and ideas L6563H 42/48 doc id 16047 rev 2 figure 61. application board 130 w-12 v adapter with L6563H, l6599a, srk2000 & x )9 & 1 5 0 5 0 5 0 5 . a a b ' *% 8- & 1< & 1< 9(5,),&$5(3,12876(&21'$5, 2 & 1; 5 . / & 3) / $ 5 . -3; ) )8 6(7$ & 1 5 . 5 . 5 . 5 5 ' // ' %$6 ' // ' // ' %=9% & x)96$ ' %=9% 4 67.1//+ ' %$6 5 1 0 -; pp ghj3,1 675, 3 & 1 9 ' // 5 . & x)96$ ' 677+/ 5 17& 56 & x) 9 4 67.1//+ ' // 5 5 & 1 & x)9 5 . 5 . & x )96$ & x)96$ 5 0 5 . -3 - 0.'6 5 5 & 1 5 5 5 0 & x )9 +6 5 5 5 1 0 9df 26&21 5 5 5 1 0 5 . 5 5 ' // 4 %&& 8 7/$,= 5 5 5 5 & x) & 3) 5 . & x )9 4 67)101 ' 1 5 . 5 . 5 0 & 1 0 5 0 5 . 5 . 5 . 5 0 5 5 9(5,&$5(6(5,(0$5& $ 5 5 5 . & 1 5 5 5 1 0 & 1; 5 . 5 0 5 0 4 %&& $''('&5(029('&5 5 . ' // 5 5 ' 1 0 & 1 9287 & x) & 3) 7 7%$ & 1 ' // & 1 & 1 & 1 -3 & 1 5 . 5 . 5 . 9287 4 67310 )3 / x '$8*+7(5%2$5' & 1 5 . 4 1 0 6*1' (1 '96 '96 *' 3*1' *' 9&& 8 65. ' %=9% 4 67310)3 & x )9< ;) 5 . +6 +($76,1 . 5 . 5 0 ' // -3; & 1 & 1 5 . & 1 & 1 0 ' %$6 5 . -3 ' 6736/$ 5 . & x )9 & 1< & 1) - 0.'6 5 . 5 . -;$ 3&%+ 2/(675, 3 5 5 & 1 5 . 5 5 & 1< ' %$6 5 1 0 & 1 & x)9 5 . 5 . 5 . 5 1 0 & 1 0 & 1 8 6)+ $ 5 5 ,1 9 &203 08 /7 &6 9)) 7%2 3)& 2. 3:0/$7&+ 3:06723 58 1 =& ' *1' *' 9&& +96 1& 8 /+ 5 5 & 1 5 . 4 %&& &66 '(/$< &) 5) 0,1 67%< ,6(1 /,1 ( *1' /9* 9&& 1& 287 +9* 9%227 ', 6 3)& 6723 8 /$ !-v
L6563H application examples and ideas doc id 16047 rev 2 43/48 figure 62. demonstration board evL6563H-650w wide-range mains: electrical schematics 9&& +6 +($7 6,1. +6 +($7 6,1. 5 . ' 1 5 . 9 & x)9 ) 7 $ 9 & q);9 df ' 6736&' 5 . 5 5 : 5 0 5 . 5 . 5 . 5 5 5 5 : & q)9 ' // - 5 5 & 1 5 0 5 . & x)9 & q);9 df 5 0 5 0 5; 5 5 . & x)9 5 . 4 67) 101 5 . 5 0 4 67) 101 ' // 5 0 5 5 - &21,1 5 0 / 72 52,'( x + 5 0 4 67) 101 & 1 5 . -3 10 a a ' ';% a a ' ';% 5 0 & x)9 & q)9 5 5 & q)9 ' // 5 5 9&& 5 17& 5 6 5 0 & x) 5 . 5 5 & x)9 5 5 & 1 & x) 5 5 : ' // 4 %& & & 3) 5 5 5 5 5 . & x) 9 & 3) ' // 5 5 & q);9 df / "" x+$ & 1 9rxw 9df 1& 571 9gf 571 9gf 9 4 %& & ,1 9 &203 08/7 &6 9)) 7% 2 3)& 2. 3:0 /$7& + 3:0 6723 58 1 =&' *1' *' 9&& +96 1& 8 /6 / 5(6 . * & 386 5 5 : 5 5 : & 3) 5 5 : / &0 p+ $ 5 . ' 6736/ $ 5 . -3 10 5 5 3: 0b6723 3: 0b6723 3: 0b6723 - &21 9&& 21 2)) *1' 3:0b/$7&+ 3:0b6723 3: 0b6723 !-v
package mechanical data L6563H 44/48 doc id 16047 rev 2 8 package mechanical data in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack is an st trademark. table 6. so16 mechanical data dim. mm min. typ. max. a 1.75 a1 0.1 0.25 a2 1.25 b 0.31 0.51 c 0.17 0.25 d 9.8 9.9 10 e 5.8 6 6.2 e1 3.8 3.9 4 e 1.27 h 0.25 0.5 l 0.4 1.27 k 0 8 ccc 0.1
L6563H package mechanical data doc id 16047 rev 2 45/48 figure 63. so16 mechanical data
ordering codes L6563H 46/48 doc id 16047 rev 2 9 ordering codes table 7. ordering information order codes package packing L6563H so16 tu b e L6563Htr tape and reel
L6563H revision history doc id 16047 rev 2 47/48 10 revision history table 8. document revision history date revision changes 22-jul-2009 1 initial release. 01-feb-2010 2 updated table 4 on page 11
L6563H 48/48 doc id 16047 rev 2 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a parti cular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. unless expressly approved in writing by an authorized st representative, st products are not recommended, authorized or warranted for use in milita ry, air craft, space, life saving, or life sustaining applications, nor in products or systems where failure or malfunction may result in personal injury, death, or severe property or environmental damage. st products which are not specified as "automotive grade" may only be used in automotive applications at user?s own risk. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2010 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - philippines - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

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